Registar
Página 5 de 85 PrimeiroPrimeiro ... 345671555 ... ÚltimoÚltimo
Resultados 61 a 75 de 1267
  1. #61
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    AMD: We will actively promote ‘Zen’ processors for server market

    Advanced Micro Devices now commands only about 2 or 3 per cent of the server market because of various reasons and the company is not going to regain its positions with the current Opteron offerings. Nonetheless, the chip designer seems to pin a lot of hopes on its “Zen” micro-architecture and will actively try to re-enter the server market with its future chips.
    “We are working very actively with our customers in the server business to introduce [Zen-based] part in the 2016 timeframe,” said Devinder Kumar at Morgan Stanley technology, media and telecom conference.

    Back in February it was reported that AMD planned to release server microprocessors powered by the “Zen” micro-architecture first and only then unveil consumer versions of such chips. The company traditionally did so for many years, therefore, the approach is not exactly something new.
    AMD understands server business pretty well since it was quite successful with its Opteron processors in mid-2000s. The company knows that it is impossible to gain share of server market by just dropping prices of central processing units, hence, AMD is working with industry partners in a bid to ensure that infrastructure for its chips is there when it is needed. Before launching new server CPUs, AMD and its allies need to design core-logic sets, mainboards, platforms, actual servers and many other things. The fact that AMD’s CFO mentions that means that the company is indeed preparing to release something which it expects to be competitive. Unfortunately, the CPU developer shares no exact plans or technical details about its upcoming projects.
    “We know the server business earlier from our history, going back to the Opteron days; we know the x86, we know 64-bit and the [Zen] core will come in 2016, the new core for the traditional x86 server space and then revenue thereafter,” said Mr. Kumar. “But it is still a little while before we get there. But we will have a core then.”

    Earlier it was reported that the first CPU to use “Zen” for client PCs will be the code-named “Summit Ridge” chip. The processor is projected to integrate up to eight cores, a DDR4 memory controller, a PCI Express 3.0 controller and feature up to 95W thermal design power. It is likely that the central processing unit will be made using 14nm FinFET process technology by GlobalFoundries or Samsung Electronics. Based on unofficial information, AMD’s “Summit Ridge” processors will hit the market in the third quarter of 2016.
    Although server chips powered by “Zen” micro-architecture are expected to hit the market earlier than desktop CPUs featuring the same technology, nothing is known about them. AMD could place two “Summit Ridge” dies one slice of substrate to get a 16-core microprocessor (like it does today with Opterons), or just create a monolithic 16-core die.
    Noticia:
    http://www.kitguru.net/components/cp...server-market/
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  2. #62
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    AMD cuts ‘Bulldozer’ instructions from ‘Zen’ processors

    Advanced Micro Devices has been talking about development of its next-generation high-performance “Zen” architecture for months now, but so far it has not revealed any details about the chips officially. Nonetheless, thanks to a recent patch for Linux we have learnt one significant detail about “Zen”: it will not support many instructions found in the current-generation processors.
    AMD recently started to enable support of its forthcoming “Zen” microprocessors in Linux operating systems. While typically patches to Linux distributives do not reveal a lot of micro-architectural peculiarities of various central processing units, this time is a clear exception. AMD explicitly revealed in the description of the patch to the GNU Binutils package that “Zen”, its third-generation x86-64 architecture in its first iteration (znver1 – Zen, version 1), will not support TBM, FMA4, XOP and LWP instructions developed specifically for the “Bulldozer” family of micro-architectures.
    Elimination of such instructions clearly points to the fact that AMD’s new micro-architecture is a complete far cry from “Bulldozer”. The company even decided to remove support of the “Bulldozer”-specific instructions to save transistors and die space for something more useful. It seems that AMD now considers “Bulldozer” a dead-end and does not want to support even promising instructions introduced in the recent iterations of the company’s micro-architectures.

    While FMA4 and XOP could boost performance in gaming, HPC and multimedia applications, a promising thing that will be missed by numerous programmers is LWP, or lightweight profiling.
    The lightweight profiling was developed to enable code to make dynamic and real-time decisions about how best to improve the performance of simultaneously running tasks, using techniques such as memory organization and code layout, with very little overhead. The LWP is a set of hardware features in AMD “Bulldozer” processors, which should be considered when designing applications.
    Noticia:
    http://www.kitguru.net/components/cp...en-processors/


    A AMD quer mesmo começar um novo ciclo e distanciar-se dos FX, para isso corta instruções que foram pensadas para esses cpu´s esperando que com isso esta nova arquitetura se torne competitiva.
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  3. #63
    Tech Membro Avatar de MAXLD
    Registo
    Mar 2013
    Local
    C.Branco
    Posts
    2,326
    Avaliação
    0
    É preciso é que as vantagens depois compensem essa remoção. Esperemos que sim.

  4. #64
    Tech Mestre Avatar de Winjer
    Registo
    Feb 2013
    Local
    Santo Tirso
    Posts
    8,783
    Avaliação
    3 (100%)
    A questão é que a Intel decidiu ficar-se pelas FMA3. Como a maioria dos criadores de aplicações e jogos seguem o que os CPUs da Intel tem, não adianta estar a gastar espaço no CPU para colocar instruções que raramente serão usadas.

    Nos Zen a AMD parece estar querer colocar à risca as instruções que a Intel coloca nos seus CPUs.

  5. #65
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    AMD’s Next Gen Zen Core Features Many New Instruction Sets And Leaves Behind Some Old Ones

    AMD’s highly anticipated Zen core will feature a plethora of new instruction sets, but will also lose some Bulldozer specific ones in the process and for good reason. This information was revealed through a patch released by AMD to ensure compatibility between the new core and Linux.

    Zen is AMD’s next generation high performance x86 CPU core. It’s being developed in tandem with its “sister” core the 64bit, ARMv8 based K12. We exclusively broke the news about Zen over six months ago when the company’s then CEO, Rory Read, revealed the code name for the core.
    AMD’s Next Gen Zen Core Features Many New Instruction Sets And Leaves Behind Some Old Ones

    Zen will succeed AMD’s last Bulldozer based CPU core, code named Excavator, in 2016. Excavator will be featured in AMD’s upcoming APU’s code named Carrizo. The Excavator CPU core has been tweaked specifically for the mobile segment. AMD states that the new core consumes 40% less power than its predecessor Steamroller. And Carrizo represents the most significant power efficiency leap the company has ever achieved with any APU.

    According to sweclockers, the new core will first make its debut to desktop processors inside the Summit Ridge family of products. Which will feature up to 8 Zen CPU cores under a frugal 95W TDP. Which indicates that the new CPU core will be highly power efficient. According to the same source the Summit Ridge family of products will debut on a new FM3 socket, will support DDR4 memory and will be built on 14nm FinFET.



    The Linux patch revealed the instruction sets that Zen will support. Zen will support all the instruction sets of previous AMD CPU cores except four specific sets introduced with bulldozer and these include TBM, FMA4, XOP, and LWP. These AMD exclusive instruction sets will no longer be supported due to their underutilization to save both area and power that can go into building more useful structures in the core.
    However the good news is that what has gone in is far more than what has gone out. AMD has implemented support for several new instruction sets in Zen. These include SMAP, RDSEED, SHA, XSAVEC, XSAVES, CLFLUSHOPT, and ADCX. Some of the mentioned instruction sets are new extensions which have been introduced by Intel with Broadwell. However the majority of the new instruction sets that Zen will support we haven’t seen or heard about anywhere else yet, not even with Skylake. So they seem to be unique to the Zen microarcthiecture.
    Michael Larabel from Phoronix states :
    It’s nice to see with Zen that AMD will support the RDSEED instruction, which Intel has added since Broadwell for seeding another pseudorandom number generator. SMAP is short for the Supervisor Mode Access Prevention and is another Intel instruction set extension already supported by Linux.
    AMD Zen also adds a new CLZERO instruction. This is a new one and “clzero instruction zero’s out the 64 byte cache line specified in rax. Bits 5:0 of rAX are ignored.”


    Noticia:
    http://wccftech.com/amd-ditching-bul...#ixzz3VEFgQsNK


    Cá estão as novas instruções que os Zen vão suportar e claramente se nota que a AMD está a aplicar as mesmas instruções que a Intel.
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  6. #66
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    AMD CPU And GPU Roadmaps For 2015-2020 Officially Emerge

    AMD shared its 5 year long GPU and APU roadmap with the world for the first time during the PC Cluster Consortium event in Osaka Japan. During the event AMD’s Junji Hayashi took the stage to reveal what AMD has got in the works for the next five years.

    The discussion revolved around AMD’s graphics IP and all the products that involve it. Including discrete Radeon graphics cards and Radeon powered Accelerated Processing Units or APUs for short. As well as AMD’s upcoming ARM ( K12 ) and it’s sister x86 CPU core ( Zen ) . In addition to AMD’s ambidextrous strategy to develop and introduce both x86 and ARM powered SOCs to the market in a pin for pin compatible platform code named SkyBridge.
    AMD CPU, APU and GPU Roadmaps Emerge

    As you’ve come to know by now AMD is planning to introduce two brand new CPU cores into the market next year. Both are 64bit capable parts but one is based on the ARMv8 architecture while the other is based on the more traditional x86 AMD64 architecture. The cores will target the server, embedded, semi-custom and client markets. Both cores will debut inside 14nm FinFET products ( CPUs and APUs ).
    If you’re in the know then so far you’ve learned nothing particularly new. The new information that has been revealed this time around is that the K12 and x86 sister core will support “many threads”. It was speculated and rumored before that AMD’s upcoming x86 and ARM CPU cores will support simultaneous multi-threading instead of clustered multi-threading which is what AMD’s current Bulldozer family (Piledriver, Steamroller and Excavator) of processors support.
    Simultaneous Multi-Threading or SMT for short is often leveraged in large CPU cores to opportunistically take advantage of the various resources in the core which are underutilized and dedicate them to an additional, slower, execution thread for added throughput. This adds to the area efficiency of the core design and reduces the effect of stalls and pipeline back pressure leading to improved resource utilization inside the core which in turn improves overall performance.
    In contrast, clustered multi-threading works by looking for opportunities to share resources between two different CPU cores, instead of doing it inside a single CPU core. The upside is savings in power and chip area by use of fewer transistors. So essentially with SMT the net result is one super fast thread and an additional much slower thread. While the CMT you get two equally and moderately fast threads. The first approach is ideal for single threaded applications, while the second approach excels in multi-threaded applications.





    It was never really confirmed nor was the extent of the multi-threading support in AMD’s upcoming cores known. So it appears that AMD’s upcoming K12 ARM core will be quite large for it support “many threads” instead of just supporting one additional thread as is the case with Intel’s high performance CPUs.
    Moving on to GPUs, Hayashi revealed that AMD will be employing a two year cadence to updating its GPU architecture inside APUs.
    AMD will introduce Accelerated Processing Units with updated GPU architectures once every two years. It should be noted that this does not mean that AMD will only be introducing new graphics products every couple of years because that’s not the case. Discrete graphics cards will follow a faster cadence, this roadmap only serves to illustrate GPU architectures in relation to APUs.
    By 2017 AMD plans to introduce what it described as a High Performance Computing APU or HPC for short. This APU will carry a sizable TDP between 200 and 300 watts. This sort of APU, AMD expects, will excel in HPC applications. Similarly powerful APUs were not attempted up to this point because they were simply not viable due to the amount of memory bandwidth required to keep such a powerful APU fed. Thankfully however stacked HBM ( High Bandwidth Memory ) will make such designs not only possible but extremely effective as well. As the second generation of HBM is 9 times faster than GDDR5 memory and a whopping 128 times faster than DDR3 memory.
    Code names for future GPU architectures unfortunately were not revealed. But we did learn through a previous leak by our friends from Sweden that AMD’s upcoming GPU architecture to debut on 16nm FinFET will be code named Arctic Islands. We’ll get considerably more detailed CPU, APU and GPU roadmaps from AMD in May during the company’s scheduled Financial Analyst Day event, so stay tuned.



    Noticia:
    http://wccftech.com/amd-gpu-apu-road...#ixzz3VsPRtOUr


    Algumas coisas interessantes estão aqui a ser reveladas, como novos cpu´s e novos gpu´s, a duvida aqui é se a AMD consegue cumprir com esses raodmaps apresentados.
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  7. #67
    Tech Mestre Avatar de Winjer
    Registo
    Feb 2013
    Local
    Santo Tirso
    Posts
    8,783
    Avaliação
    3 (100%)
    São apenas rumores, por isso já sabem....

    AMD x86 Zen Based High-Performance APU Detailed – Rumored To Feature 16 Cores, 16 GB HBM Memory, Greenland iGPU and DDR4 Memory Support


    Note: This article is tagged as a rumor, the information being reported shouldn’t be considered as official confirmation until an official announcement is made by AMD.Fudzilla has detailed an interesting product which they have been talking about since the last couple of weeks. According to their sources, AMD might be up to something big with their next generation APU design that will be featuring the x86 Zen core architecture and a GCN enabled integrated graphics compartment, allowing true high-performance accelerated processing units for the HPC/Server markets.

    AMD x86 Zen and GCN Based High-Performance APU Rumored To Featured HBM and DDR4 Memory Support

    The rumor is too much to consume and may be entirely fabricated as a the design mentioned in the single slide is far too imaginary for AMD who are developing nothing close to the product detailed. The only two platforms which AMD is launching for consumers in the future include Carrizo on notebook and Godavari on the desktop front. This leaves their x86 Zen architecture to end up inside server processors by late 2016 along with a high-performance consumer platform. The slide from Fudzilla might be for a product that doesn’t exist or if existed, may launch far in the future.
    There’s no exact name given to the APU mentioned in the slide, it’s just the technical part being shown that lists down the architectural details. The product is distinctly mentioned to be used in the server/HSA market which AMD is focused towards with their upcoming parts. The x86 Zen being a SMT design will boast 16 high performance Zen cores and 32 threads (two threads per core). The Zen cores are backed by 512 KB of L2 cache and a quad module of these cores share 8 MB of L3 cache which puts the total available L2 cache to 8 MB and LLC (L3) cache to 32 MB. Two technologies, AMD Crypto Co-Processor and Secure Boot indicate that it is most likely a product aimed towards the compute HSA sector and this might be believable since the APU sounds a bit too much for a mainstream platform which gets $150 US APU models.
    Ok this might get a bit crazy from this point onward, the rumor alleges that the APU will further feature the Greenland GPU which has the next generation GCN architecture and support HBM memory. Known as the Greenland Graphics and Multi-Media Engine, the block diagram reveals that it takes a large portion of the die space and has its own dedicated 16 GB of HBM memory that pumps out 512 GB/s bandwidth. The GPU also has 1/2 rate double precision compute available to it which is a first in the APU department and also points to ECC, RAS and true HSA support.
    AMD is also putting a Quad channel DDR4 memory controller on the said APU design which will allow support of up to 256 GB memory per channel (SODIMM/UDIMM/RDIMM/LRDIMM). Basically, there’s 2 DIMMs supported per channel so we are looking at 1024 GB of DDR4 memory support with speeds rated at 3200 MHz. Furthermore, the APU has 64 PCI-e 3.0 channels and the lanes can be dedicated to either SATA Express and SATA which take up 16 lanes (2 for SATA-E and 14 for SATA III). The coherent link will allow AMD to fused and interconnect both the CPU and GPU along with coherency in the sharing of the large memory pool which include both cache, HBM and system memory (DDR4). We have already seen Intel’s Xeon Phi Coprocessor featuring a similar design by adding Stacked DRAM and adding support for DDR4 memory on a single monolithic package.








    So after this long summary of details for an unknown product, the first question that comes to mind would be, is such a design even possible? Well its very much possible and given the recent details revealed by AMD, its very much likely that one day we might see an APU as detailed by Fudzilla. The question that should be asked is not whether we will see such an APU but when we will see such an APU. If you recall about the HPC APU, we have just heard about such design recently in AMD’s 2015-2020 roadmaps which were secretly shown off in a conference held in Osaka, Japan. A closer look at the roadmap mentions the replacement to Toronto based Opteron APUs coming in-between 2016-2017. That’s around the same time we get to see Zen and the part is mentioned as HPC 64-bit APU. Additional details reveal that the design will take its harmonized design from a FirePro level graphics next core GPU and a server level x86 APU which users several cores. This HPC APU will have TDPs close to 300W and is suited entirely to the compute market. This is the kind of news that does get me excited even if it’s not for the consumers, we can expect that in the future we will have APUs of the same performance-level close to us. You can submit your saying on the rumor in the following poll whether you believe its true or not:

  8. #68
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    AMD makes ‘significant investments’ in server CPUs

    Advanced Micro Devices continues to express confidence that its next-generation high-performance general-purpose processing cores – known as “K12” and “Zen” – will be successful on the market of servers. After exiting the market of micro-servers by shutting down SeaMicro, AMD now focuses on development of high-performance microprocessors for x86 and ARM-powered machines.
    “The x86 server market is a very large market and it is one, where we have historically been successful,” said Lisa Su, chief executive officer of AMD, in the company’s quarterly conference call with investors and financial analysts. “I do believe that it is an area that we can grow over the mid-term.”
    AMD is expected to release server-class Opteron processors based on “Zen” and “K12” cores in 2016. Nothing particular is known about these upcoming Opteron chips except of the fact that they will be made using 14nm or 16nm FinFET process technologies. AMD claims that it is increasing investments in its enterprise, embedded and semi-custom (EESC) business unit in order to develop appropriate solutions for servers. Keeping in mind the fact that design of FinFET chips alone costs tens to hundreds millions of dollars – roughly three times more than design of chips with planar transistors – AMD simply has to increase its investments in order to develop its new server chips.

    AMD realizes that in the modern world many owners of large cloud datacenters, such as Amazon Web Services or Facebook, require semi-custom and full-custom chips to run their servers. As a result, in addition to developing standard processors, the company is also designing special-purpose hardware blocks (e.g., hardware accelerators for security, storage, networking and virtualization applications), which could be used for semi-custom system-on-chips for servers.
    “We are making significant investments in standard server processors as well as in the IP for semicustom opportunities,” added Ms. Su. “Think of it as x86, ARM, the other technologies required to make competitive server products.”
    Although AMD continues to talk about its server opportunities, it does not reveal any particular plans about its new Opteron chips, such as availability timeframes. All we know about AMD’s server strategy today is that the company wants to address cloud and enterprise datacenters as well as networking segments with standard and semi-custom products.
    Noticia:
    http://www.kitguru.net/components/cp...m-server-cpus/
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  9. #69
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    The next generation Opteron has 32 Zen x86 cores



    No APU, 16MB L2, 64MB L3 cache
    We recently showed you a new 16 Zen core next generation processor with Greenland integrated graphics and DDR4 support.

    This part definitely sounds interesting but we got an update on the 2016 Opteron server market parts. The next generation Opteron won't have an integrated graphics part but it will have up to 32 Zen x86 cores with 64-thread support. Unlike the highest end compute HSA part that comes with Greenland HBM graphics, the next generation Opteron doesn't have any integrated graphics. The Opteron needs all the silicon space for the L2, L3 cache as well as its Zen x86 cores.
    Just like the 16 Zen core high performance market APU, each core has 512KB of L2 cache and four processors share 8MB L3 cache. The highest end part will come with eight clusters of 4 cores and if you do the math this server oriented CPU will come with 64GB of L2 cache and 16MB of L2 cache for its CPU cores.
    A few other notable features for the next generation server parts include a new platform security processor that enables secure boot and crypto coprocessor. The next generation Opteron has eight DDR4 memory channels capable of handling 256GB per channel. The chipset supports PCIe Gen 3 SATA, 4x10GbE Gig Ethernet and Sever controller HUB. Of course, there will be a SMP, dual socket version.
    The next generation Opteron will have 32 CPU cores in its highest end iteration, and we expect some Stock Keeping Units (SKUs) with fewer cores than that for inexpensive solutions.
    In case AMD comes to market with this part on schedule, and if the Zen core ends up performing as expected, Intel might finally get some competition. Let's just hope for AMD's sake that this server CPU is coming in 2016, sooner rather than later.
    We can only on possible Zen-based FX parts for high-end desktops, or the manufacturing process for Zen chips, but at this point we cannot confirm FX parts are coming, and whether or not they will be manufactured in 14nm.
    Noticia:
    http://www.fudzilla.com/news/process...-zen-x86-cores
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  10. #70
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    AMD x86 16-core ZEN APU to fight Core i7



    Greenland APU gives it the necessary firepower
    AMD mini cores and modular designs backed by HBM graphics and the upcoming Greenland GPU core might be a winning combination for AMD.

    The flagship desktop Zen chip, that still doesn’t have a codename we can mention, should be coming in 2016 in 14nm GlobalFoundries' high performance manufacturing process. This is a successor to the Richland / Carrizo APUs and the highest end part is aiming to give the seventh generation Intel Core i7 (Cannonlake 10nm) run for its money.
    At this point it is obviously too early to announce any winners, it will come down to how efficient AMD's 14nm APU is versus next generation Core i7 parts. The instructions per clock will be a relevant factor in this equation, but if AMD comes close to Intel's performance, it will be a huge heap forward for the company.
    There is no doubt that Greenland graphics will end up better than Intel Iris graphics that will be the part of Skylake 14nm desktop parts, and most likely the Cannonlake 10nm Core variants expected in 2016.
    AMD x86 Zen, DDR4, Greenland, HBM core FTW

    AMD's Zen based APU will be available in more than just the 16-core version, since this is a modular design and a quad-core with 2MB L2 and 8MB L3 is also possible, octa-core with 8x512KB and 2x8MB L3 cache should be in the cards too.
    The fact that AMD uses DDR4 will additionally help its cause and it might win back some desktop market share. AMD still has a lot of engineering power that can surprise, and it will all come down to execution.
    One can only hope that AMD x86 16-core Zen APU and its derivatives are coming by mid-2016 (let's say Computex 2016) but this is speculation and nothing that we can confirm or deny. In case Zen X86 performs as well as K8 (blast from the past), this might be a big break that many fans were hoping for, as K10 Barcelona / Shanghai were not as great as many hoped for. K10 started the whole downward spiral for AMD CPUs and let's hope that Zen can reverse this trend.
    Noticia:
    http://www.fudzilla.com/news/process...-fight-core-i7


    Era bom que a AMD começasse a dar alguma luta... mas um APU competir com i7, não me parece que seja bom de mais para ser verdade.
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  11. #71
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    32 core Opteron supports 2P sockets



    140W max TDP
    Opteron processors based on the Zen architecture are coming in 2016 (hopefully) and we expect to see them using 14nm GlobalFoundries' manufacturing process.

    What we can confirm is that the 32-core processor actually uses 8 cores per die on four die ona MCM (Multi Chip Module) socketed LGA design.
    Each MCM module with 8 cores has two memory channels with up to 2 DIMMs per channel. The maximum TDP for the Opteron Zen 2016 series is set at the standard 140W and there will be a 120W TDP SKU, as well as lower TDP parts.
    AMD also has something called Combo Links that combines 8-16 bit links (2 per die) and this link can take the form of xGMI, PCIe, SATA, SATA Express, 10Gbase-KR or SGMII. There will be boards with 1P socket configurations and 2P socket configurations for more than one LGA socketed processor.
    Dual socket 2P motherboards support four AMD External Global Memory interconnect xGMI links, or one per die. The standard 2P board comes with maximum of 64 PCIe lanes per socket, 16 SATA laners, four 10GigE and four 1GigE per socket.
    AMD relies on coherent interconnect for 2-socket configurations that should enable faster inter-socket communication between two CPUs. The specification looks promising, but it remains to be seen if the instruction per clock rate will improve significantly, and how well can these eight dies interconnected in one MCM package perform against the competition. Servers are a huge growth and return to profitability opportunity for AMD, but Intel won't give this highly profitable market without a serious fight.

    The main question is if AMD can make it on time with Zen, if it can deliver these Opterons in volume before Intel moves to newer architectures and nodes.
    Noticia:
    http://www.fudzilla.com/news/process...rts-2p-sockets
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  12. #72
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    32-core AMD Opteron to feature quad-die MCM design

    Advanced Micro Devices will continue to use multi-chip-module design for its upcoming AMD Opteron processors. This should greatly help the company to reduce its development and manufacturing costs, but may affect performance of its central processing units for servers.
    The forthcoming AMD Opteron processors with up to 32 cores based on the “Zen” micro-architecture will consist of up to four eight-core dies known as “Summit Ridge”, reports Fudzilla. Each “Summit Ridge” chip has a dual-channel DDR4 memory controller, therefore, the new Opteron chips will feature an eight-channel memory sub-system. Nowadays AMD uses two eight-core and six-core dies in order to make 16-core and 12-core Opteron processors, respectively. Other developers of server chips, such as IBM, also use MCM approach to build high-end server processors.

    Design of an advanced microprocessor that will be made using a FinFET process technology costs north from $150 million without the cost of photomasks needed for production. It makes a great sense for AMD to use “Summit Ridge” dies for desktops and workstations for its upcoming Opteron chips for servers. However, topology of the new AMD Opteron processors and dual-socket platforms will get very complex because of the multi-die MCM implementation.
    Each “Zen” core in the new AMD Opteron systems will have to maintain cache coherency with other cores no matter where they are physically located. As a result, AMD will have to introduce an ultra-high-bandwidth interconnect technology for its upcoming chips that will be fast enough to maintain cache coherency and provide unified memory access to all processing cores.
    AMD’s next-generation Opteron processors will feature a land grid array (LGA) packaging as well as up to 140W thermal design power.
    Noticia:
    http://www.kitguru.net/components/cp...ie-mcm-design/
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  13. #73
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    New leaked AMD Zen slide



    High performance monster

    The block diagram of the new AMD Zen core has found its way onto the Planet 3 news group.

    If the leak is accurate it compares the Zen, on the right, with AMD's upcoming and last Clustered Multithreading / CMT CPU core code named Excavator.
    Excavator is the last of AMD's Bulldozer family of cores and it will appear with AMD's Carrizo APU, which AMD claims will be the most power efficient mainstream APU.
    Zen takes a more traditional AMD CPU layout similar to Phenom. There appears to be one integer cluster in a Zen core while there are two as in the Excavator. Bulldozer had a high integer throughput at the expense of floating point performance.
    In Zen AMD uses a single fetch and single decode unit on the front end which is also a step back from Steamroller's double decoders that were introduced with.
    It appears then that Zen will have a higher single threaded integer and floating point performance compared to Excavator and Bulldozer.
    AMD has introduced a floating point that's twice as wide as that of Excavator. Featuring two FMAC 256-bit units. These will probably fuse and process 512-bit AVX floating point instructions. In Bulldozer this is carried out by two 128-bit FMAC units. They can process one 128-bit SIMD instruction each per clock or fuse to process a single 256-bit AVX instruction per cycle. So it looks like Zen's FPU will go the same way and allow both FMACs to cooperate and process 512bit AVX instructions.
    Zen enables 512bit AVX support, and with the wider floating point unit can process less complex instructions at double the rate of Excavator. Historically AMD did well with floating point performance until Bulldozer so this will be a return to form.
    Zen features a 50 per cent wider integer pipeline vs a single Excavator core. Which will also dramatically improve the single threaded / per core performance of Zen.
    Coupled with a more advanced 14nm process from Samsung/Globalfoundries the net result should be a significantly faster, leaner, smaller and more power efficient CPU core than Excavator.
    We are expecting to see the products in the shops next year with more official information coming out in a couple of weeks.
    Noticia:
    http://www.fudzilla.com/news/process...-amd-zen-slide
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  14. #74
    Tech Ubër-Dominus Avatar de Jorge-Vieira
    Registo
    Nov 2013
    Local
    City 17
    Posts
    30,005
    Avaliação
    1 (100%)
    AMD Zen architecture processors are true quad-core CPUs

    A number of slides about AMDs upcoming ZEN APU architecture have been shared on AMDs Financial Analyst day. Zen is the code name for a new 14nm x86 micro-architecture being designed by AMD from the ground up and is expected to launch in 2016–2017
    ZEN basically will be the equivalent of what phenom is/was back in the days but much more powerful and energy efficient.
    Initial findings indicate that that Zen may use a SMT-style micro-architecture, indicating SMT on AMD's cluster core which traditional usage of clustered multi-threading. On the server side of this that means you can combine multiple processors on one PCB. The zen architecture will be built on a 14 nanometer process and feature DDR4 support and 95W TDP, fabrication would happen at GlobalFoundries 14 nanometer FinFET node.
    If you look at the slides then you will notice that Zen resembles the 'Stars' core design that AMD launched with its Phenom series, but way more powerful. The module design that you see on the APUs for example are not present here. Each 'clucstre; is its own core, and on an APU each cluster/module has two cores. So each core should be spicy in terms of performance in what seems to be a very parallel approach.
    The new processor series will support both DDR3 and DDR4 over the integrated memory controllers as well as PCI-Express 3.0, this will obviously vary per motherboard Each core will get a dedicated 512 KB L2 cache and there is a shared 8MB L3 pool. There are four cores.
    A new slide shows more detailed specifications, Zen will definitely get four cores sharing a good 8 MB of L3 cache. So again, the four units are not clusters or modules with two cores per module, this is a pure quad-core unit, and thus the cores share no hardware components with each other, aside from the L3 cache.
    With an expected launch time frame of 2016 it will be interesting to see if four cores are enough to tackle Intel, currently their Haswell-E design already is at 8 cores for the consumer market, with each core being twice as fast as AMDs current architecture (per core).
    Noticia:
    http://www.guru3d.com/news-story/amd...core-cpus.html
    http://www.portugal-tech.pt/image.php?type=sigpic&userid=566&dateline=1384876765

  15. #75
    Tech Mestre Avatar de Winjer
    Registo
    Feb 2013
    Local
    Santo Tirso
    Posts
    8,783
    Avaliação
    3 (100%)
    A intel foi buscar inspiração aos Pentium 3 para fazer os Core. Agora a AMD vai buscar inspiração aos phenom 2, para fazer os Zen.
    A parte mais engraçada foi que muita gente,quando se viu os FX, disse que mais valia pegar nos phenom2 e actualiza-los, do que andar com a arquitectura bulldozer.

 

 
Página 5 de 85 PrimeiroPrimeiro ... 345671555 ... ÚltimoÚltimo

Informação da Thread

Users Browsing this Thread

Estão neste momento 1 users a ver esta thread. (0 membros e 1 visitantes)

Bookmarks

Regras

  • Você Não Poderá criar novos Tópicos
  • Você Não Poderá colocar Respostas
  • Você Não Poderá colocar Anexos
  • Você Não Pode Editar os seus Posts
  •