MIPS Warrior I6400 (64 bits CPU)

[Winjer]

http://images.anandtech.com/doci/8457/warrior%20core%20types_575px.JPG


One of ARM’s most tangible business advantages is its offer of both CPUs and GPUs to SoC designers. Anyone with experience in business to business relationships knows just how complex forming and maintaining a mutually beneficial collaboration can be. Setting up contracts, forming rapport, defining goals, and even just understanding documentation and technical content formatting all takes time. Unless there is significant benefit to investing in two different relationships and technologies, it is simpler (read: cheaper) to single source contributing components of a design. There are down sides of single sourcing (see Boeing 787 battery fiasco), but depending on a business’ capacity for risk, the savings are undeniable. Especially when ARM undoubtedly offers bundle pricing promotions.
When Imagination Technologies acquired MIPS Technologies in 2012 for $100 million, their goal was very clear – attack ARM. Imagination’s GPU business was already wildly successful, with design wins in a bevy of high end mobile devices including those from Samsung and Apple. Adding the CPU cores from MIPS, with their decades of history designing and licensing IP, strategically positioned Imagination opposite ARM’s licensing business. Imagination’s executives have also stated they are prepared to offer aggressive IP bundling discounts.
Looking at Imagination’s product, press, demos, and interviews, it appears they are not (yet?) positioning MIPS cores to combat ARM cores at the high end of the market. Rather, they appear focused on being a viable alternative to ARM in multi-threaded and low power workloads. In fact, the vast majority of MIPS cores are currently used in network infrastructure where threading and power efficiency are paramount.
Today MIPS is announcing a major launch: the Warrior I6400 core. Based on the 64-bit MIPS64 instruction set (release 6), the Warrior I6400 core is the middle-class CPU core in a family of three, each targeting a different point in the power/performance curve. Imagination is releasing the I6400 core last, which is at the middle of the pack balancing performance with power. Imagination has already released their high-end P56xx series and low-end M51xx series.



Ler mais: Anandtech - MIPS Strikes Back: 64-bit Warrior I6400 Arrives (http://www.anandtech.com/show/8457/mips-strikes-back-64bit-warrior-i6400-architecture-arrives#comments)

Uma luta a 3 entre ARM, X86 e MIPS, parece interessante....

[LPC]

Boas!

Que tipo de linguagem é usada pelo MIPS?
Em termos de compatibilidades e velocidade é o maior entrave...

Parece-me a mim que ARM está mais avançado que a MIPS... No entanto ainda ambas tem muito que andar até apanhar o x86 em termos de performance...

Com os meus melhores cumprimentos,

LPC

[Jorge-Vieira]

Imagination To Give Universities Free And Open Access To MIPS Architecture

http://media.bestofmicro.com/O/L/493365/gallery/MIPSfpga-architecture_w_600.png (http://www.tomshardware.com/gallery/MIPSfpga-architecture,0101-493365-0-2-12-1-png-.html)Today, Imagination announced that it's going to open up its MIPS architecture for universities interested in teaching their students how to build microprocessors as part of the company's Imagination University Programme (IUP) called "MIPSfpga." Through this program, Imagination is offering a fully-validated MIPS CPU RTL (register transfer language) along with all the needed teaching material in a complete package.

If adoption is high (and it could be) we could see new generations of students that know how to program MIPS processors. This could help Imagination in two ways. The company itself will have access to a wide base of potential employees, and it could also see a bigger push for adoption of MIPS processors within other companies where those students may find future employment.
Imagination isn't actually open sourcing its IP here. The company is still an IP-vendor after all, and open sourcing the IP would leave it with no revenue. The license does give some freedom to university professors, though. They can use the architecture as they wish (which includes using a simulator), but they can't actually build a silicon chip with it. The universities can go as deep under the hood as they like, but if they want to patent certain changes to the architecture, they will have to talk to Imagination first.
What the universities will get includes:



a MIPS-based MicroAptiv CPU
MIPSfpga Fundamentals set of teaching materials (available soon)
MIPSfpga Advanced - even more in-depth teaching materials (available later)

CPU architecture is usually taught in courses for electronic engineering, computer science, and computer engineering. So far, professors and students haven't been able to fully study the obfuscated code of the MIPS architecture, which has remained proprietary until now. Imagination is now offering universities the opportunity to study a MIPS CPU from the ground up, free of charge.

There are other CPU architectures such as RISC-V (http://riscv.org/) that are fully open source, but these haven't yet enjoyed wide adoption. Until they are used for commercial purposes, they probably only offer so much value as a classroom tool, either.
MIPS also has a strong academic background, having been invented at Stanford University in the early 1980s and having been used since as a teaching architecture of choice because of its simpler RISC architecture.

"It's been more than 30 years since we created the MIPS architecture at Stanford University. I am pleased to see MIPS rejuvenated under Imagination's care, and to see Imagination rolling out this exciting new program that brings MIPS back to academia in a big way. With its pure RISC architecture based on efficiency and simple extensible design principles, MIPS is an ideal architecture for teaching and studying CPU design. Professors and students alike can benefit from the ability to study MIPS RTL code and explore a real MIPS CPU."
– Dr. John L. Hennessy, Office of the President, Stanford University
These days, RISC CPUs are much more complex than they used to be, which is why many universities have complained that mainstream CPUs are too complex for university classes. This is why Imagination started its own campaign to talk to dozens of universities across the world and get feedback on what an appropriate CPU design would look like for the purposes of teaching. That's how the company got to use a simpler version of its microAptiv CPU (used in microcontrollers).
http://media.bestofmicro.com/O/M/493366/gallery/microaptiv_w_600.png (http://www.tomshardware.com/gallery/microaptiv,0101-493366-0-2-12-1-png-.html)With the materials they will get from Imagination, students can learn to develop their own CPU and then take it through debug while it's running on an FPGA platform.
The MIPSfpga has already been adopted by universities such as Harvey Mudd College, Imperial College London, University College London, and the University of Nevada.
To access the MIPSfpga, academics will have to register (http://community.imgtec.com/university/) to the Imagination University Programme. Then, starting in June, they will get a click-through agreement, and more teaching material will be available later.



Noticia:
http://www.tomshardware.com/news/imagination-mips-open-access-universities,28999.html

[Jorge-Vieira]

China’s Loongson Creates MIPS Processor That Can Run x86 & ARM Code

A challenge some software developers must face is having to support more than one architecture - be it x86 (http://hothardware.com/tags/x86), ARM (http://hothardware.com/tags/arm), or something else. Wouldn't it be great, then, if one processor could support more than one of them at once, potentially allowing developers to target just one base architecture? China's Loongson seems to agree, offering its 3A2000 and 3B2000 processors as proof.
While this design might make you think that these chips are targeted at mobile (http://hothardware.com/tags/mobile) devices, they're actually designed for desktops and workstations, as well as things like network routers. The 3B2000 could be used in dual or quad CPU servers. Loongson apparently really means business here.

http://hothardware.com/ContentImages/NewsItem/34962/content/Loongson_Processor.jpg To add x86 and ARM support, Loongson makes use of a binary translation layer, which immediately makes it seem as though this is not going to be a high-performance option. Ideally, there'd be dedicated chip space for x86 and ARM dies, but it's just unrealistic given its complexity. This implementation could also help Loongson avoid legal issues, depending on how it's being done.
If these chips take off in any way, you can be sure that ARM and Intel will be investigating to find that out for themselves. This isn't the first time Loongson has faced questionable legal predicaments; when it launched its first chips, it had to leave out some patented instructions. It wasn't until an agreement was struck up with MIPS Technologies that Loongson's chips became appropriately "MIPS-based".
Legal questions aside, it's interesting (but not too surprising) that this kind of design is possible. If the chips are able to deliver decent ARM and x86 performance, they could actually prove quite useful in some instances. Perhaps not surprisingly, taking advantage of this translation layer will require Linux (http://hothardware.com/tags/linux), naturally with a MIPS-based distro.







Noticia:
http://hothardware.com/news/chinas-loongson-creates-mips-processor-that-can-run-x86--arm-code#ixzz3kwqnxUfR

[Jorge-Vieira]

Imagination adds three chips to MIPS Warrior CPU family

Imagination Technologies says that its MIPS Warrior CPUs are gaining momentum as it gets more design wins and businesses see and experience them in action. Warrior CPUs range from high end processors to embedded SoCs and are increasingly found in shipping products. Unique features such as hardware multithreading, OmniShield (http://imgtec.com/platforms/omnishield/) multi-domain security, and others, are key to MIPS Warrior design wins, say Imagination Tech.
To maintain business momentum and address growing demand three new MIPS Warrior CPUs are being introduced (http://blog.imgtec.com/mips-processors/extending-the-mips-warrior-cpu-family); the high performance 64-bit P-class MIPS P6600 CPU and the performance-embedded 32-bit M-class M6200 and M6250 solutions.
MIPS P6600
The MIPS P6600 (http://imgtec.com/mips/warrior/p-class-p6600-multiprocessor-core/) CPU offers a straightforward upgrade to customers looking for a high-performance, 64-bit P-class Warrior CPU (it is an evolution of the 32-bit P5600 CPU). It implements the MIPS64 Release 6 architecture and delivers peak performance whilst minimising chip size and power consumption. Imagination foresees its deployment in mobile, home entertainment, networking, and HPC, plus industrial and embedded computer solutions. This new chip has already been licensed (http://imgtec.com/news/press-release/mips-cpus-continue-to-push-boundaries-from-low-to-high-end/) for applications including high-performance computing and advanced image and vision systems.
http://hexus.net/media/uploaded/2015/11/ea74ae3a-3c29-4c00-8722-4c7af1025d8a.png
Users benefit from "a clear-cut boost in real-world workloads," thanks to best-in-class branch prediction and MIPS' load/store instruction bonding mechanism. The chip supports full hardware virtualization and enhanced security features. System designers can use the new P-class Warrior CPU in configurations that range from single to hexacore clusters.
MIPS P6600 key features


High-performance 64-bit MIPS Warrior CPU based on a 16-stage multi-issue Out of Order (OoO) pipeline implementation, delivering outstanding computational throughput and area efficiency
Integrated compiler-friendly 128-bit MIPS SIMD Architecture (MSA) support for efficient parallel processing of vector operations in multimedia applications
Sophisticated branch prediction with fully associative Level 1 BTB (branch target buffer) and an improved Level 2 cache sub-system
Full hardware virtualization support and Imagination’s OmniShield technologies for enhanced security and reliability in a wide range of applications

MIPS M6200 and M6250
Joining Imagination's popular M-class family are the MIPS M6200 and M6250 (http://imgtec.com/mips/warrior/m-class-m6200-and-m6250-processor-cores/), providing a broader M-class roadmap for "high-performance deeply embedded designs". Imagination foresees these processors being deployed in wired/wireless modems, GPU supervisor processors, flash and SSD controllers, industrial and motor control, advanced voice processing and others.

The MIPS M6200 and M6250 are based upon the MIPS32 Release 6 architecture and are capable of operating at 30 per cent higher frequencies than other members of the family. Looking at their differences the M6200 is tailored for devices that run real-time operating systems while the M6250 is designed for devices requiring Linux capabilities.
<tbody>
http://hexus.net/media/uploaded/2015/11/fbc2dfdc-5b8b-4961-9da4-d3892f095052_resized_330x269.png (http://hexus.net/media/uploaded/2015/11/fbc2dfdc-5b8b-4961-9da4-d3892f095052.png)
http://hexus.net/media/uploaded/2015/11/f8eb614a-af2c-4113-b376-a98dd0359792_resized_330x293.png (http://hexus.net/media/uploaded/2015/11/f8eb614a-af2c-4113-b376-a98dd0359792.png)

</tbody>


MIPS M6200 MCU & M6250 MPU key features

Low-power, compact 32-bit CPUs based on a 6-stage pipeline implementation, enabling 30% higher frequencies versus the MIPS microAptiv CPU for similar implementations
Integrated DSP and SIMD functionality to address signal processing requirements of such applications as industrial/motor control, voice processing and more
Support for microMIPS r6 Instruction Set Architecture (ISA) for superior code compression and reduced memory footprint
Data integrity features, including ECC and parity protection
AMBA APB debug interface enabling JTAG, multi-core and mixed core debugging
M6200 MCU:
Includes a memory controller for tightly coupled 64-bit Instruction/Data SRAM
A memory protection unit enables program/data security
M6250 MPU:
Includes a memory controller for Instruction/Data L1 cache and optional tightly coupled ScratchPad RAMs (SPRAMs)
A Memory Management Unit (MMU) supports virtual memory, enabling full support for Linux and other high level operating systems
40-bit eXtended Physical Addressing (XPA) support
AMBA AXI3 Bus Interface Unit

You can read more about the new MIPS processors, and the Release 6 architecture behind the designs, in Imagination's blog (http://blog.imgtec.com/mips-processors/extending-the-mips-warrior-cpu-family) post about the new Warrior CPUs. The M6200, M6250 and P6600 are all available now, just contact

Noticia:
http://hexus.net/tech/news/cpu/87968-imagination-adds-three-chips-mips-warrior-cpu-family/

[Jorge-Vieira]

MIPS-Based CPU, Debian 8 Underpin Russian T-Platforms' All-In-One PC

http://media.bestofmicro.com/0/E/563774/gallery/Tavolga_Terminal_TP-T22BT_KM_w_450.jpg (http://www.tomshardware.com/gallery/Tavolga_Terminal_TP-T22BT_KM,0101-563774-0-2-9-1-jpg-.html)Russian company T-Platforms announced that it will start selling an all-in-one PC with the (also Russian) Baikal-T1 (http://www.tomshardware.com/news/baikal-t1-mips-cpu-omnishield-support,29178.html) chip, which is based on Imagination’s MIPS instruction set architecture. The system will run the latest version of Debian 8, which is one of the more popular Linux distributions out there.
The MIPS-based Baikal-T1 processor was announced last year, after the Russian government signaled that it doesn’t want to rely on American Intel and AMD chips as much. The Baikal-T1 is a dual-core 1 GHz P5600 CPU (apparently underclocked from the original 1.2 GHz frequency). According to Imagination, it has one of the highest performance/MHz (http://blog.imgtec.com/mips-processors/mips-p5600-cpu-sets-new-performance-record) and performance/Watt scores.
The Tavolga Terminal TB-T22BT (http://www.t-platforms.ru/products/corp/tavolga-terminal-tp22bt.html), which is the name of T-Platforms’ all-in-one PC, includes a 21.5-inch IPS display with Full HD resolution, up to 8 GB of DDR3 RAM and optional storage capabilities that range from 8 to 64 GB of nonvolatile memory. Four USB 2.0 ports and one 1,000 Mbps Ethernet port are also supported.
The T-Platforms Tavolga PC is available for pre-order right now, with shipping scheduled for the second quarter of 2016. The company also plans to release a more compact PC that doesn’t come with an integrated display.
http://media.bestofmicro.com/0/F/563775/gallery/sf-bt1_w_450.jpg (http://www.tomshardware.com/gallery/sf-bt1,0101-563775-0-2-9-1-jpg-.html)The company also announced the new SF-BT1 (http://www.t-platforms.com/products/dev/sf-bt1.html) computer-on-module (COM) system that incorporates the Baikal-T1 SoC and targets device vendors who want to create high-performance IoT platforms, embedded control systems, industrial automation, healthcare or networking equipment.
The Baikal-T1 chip supports Imagination’s OmniShield (http://www.tomshardware.com/news/imagination-omnishield-hardware-security-zones,29138.html) security features, which enable applications to be isolated in their own secure domain. It also supports the prplSecurity framework, which is a collection of open source APIs that provide hardware-level security controls such as root of trust, secure boot, secure hypervisor and secure inter-VM communications.
Using these features, the prpl Foundation, started by Imagination, demonstrated three different Linux-based operating systems running in parallel on the SF-BT1 module at full performance and isolated from each other in highly secure domains.

Noticia:
http://www.tomshardware.com/news/t-platforms-aio-pc-mips-baikal-t1,31324.html